Semiconductor memory device having booster circuits

ABSTRACT

A semiconductor memory device performs a normal boost operation and increases access speed of the operation. The semiconductor memory device includes: a plurality of memory cells; a plurality of word lines to which voltages are applied to select the plurality of memory cells; a decoder that selects one of the plurality of word lines based on an address signal representing an address of one of the plurality of memory cells to be accessed; a control circuit that outputs an activated control signal and an deactivated control signal according to a transition of the address signal; and a booster that has a plurality of booster circuits including first booster circuit and second booster circuit. The first booster circuit is connected to the decoder and supplies boosted voltage to a selected word line based on the activated control signal. The second booster circuit is input the deactivated control signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device. Moreparticularly, the present invention relates to boosting voltage of aword line of a semiconductor memory device.

2. Description of the Background Art

In recent years, demand for nonvolatile semiconductor memory devicesincreases. As such a semiconductor memory device, an electricallyerasable and programmable read only memory (hereinafter referred to asEEPROM) such as a flash memory is known. In EEPROM, a plurality ofpotentials that are different from a potential of power supply suppliedfrom outside of EEPROM are generated, a voltage of a word line areboosted by means of these potentials, so that EEPROM performs operationssuch as electrically writing, reading, erasing, and the like of data.

Japanese Laid-Open Patent Publication No. 6-28876 (Japanese Patent No.3161052) discloses a configuration of a nonvolatile semiconductor memorydevice which boosts a voltage of a word line. More specifically, FIG. 1Ais a conventional circuit diagram in which the voltage of a word line isboosted. FIG. 1B is a timing chart of the circuit in FIG. 1A. Anoperation of the circuit will be described below with reference to FIG.1A. Whether the voltage of the word line is boosted or not, i.e.,whether the word line is selected or not is determined by examiningwhether all internal row address signals are at high levels or not. Whenat least one of the internal row address signals is at low level,potential of node 89 becomes ground level. In this case, the word lineis in non-selected state. On the other hand, when all the internal rowaddress signals are at high levels, the potential of node 89 is equal tothat of node 88, and the word line is in selected state.

Before the word line is selected to boost the voltage of the word line,the circuit receives from an address transition detector (ATD) circuit(not shown) a high-level ATD signal that representing that an address tobe accessed is subjected to transition. As a result, an output frominverter 86 becomes low level, and charge of capacitor 87 connected tonode 88 is started. This charging is performed in a period of time inwhich ATD signal is at high level. The operation timing is as shown inFIG. 1B. When ATD signal becomes low level, boosting the voltage of theword line is started. At this time, the voltage level of node 88 reachesVcc which is equal to power supply voltage, and the charging has beencompleted. Therefore, the voltage of the word line can be boosted.

In order to increase speed of an access operation of the semiconductormemory device, the time required to charge capacitor 87 must beshortened. In other words, the period of time in which ATD signal is athigh level must be shortened. However, when the period of time isshortened, the time required to charge capacitor 87 is insufficient, anda boost operation cannot be normally performed.

SUMMARY OF THE INVENTION

It is an object of the present invention to perform a normal boostoperation while increasing the speed of an access operation in asemiconductor memory device.

According to an aspect of the present invention, the semiconductormemory device includes: a plurality of memory cells; a plurality of wordlines to which voltages are applied to select the plurality of memorycells; a decoder that selects one of the plurality of word lines basedon an address signal representing an address of one of the plurality ofmemory cells to be accessed; a control circuit that outputs an activatedcontrol signal and an deactivated control signal according to atransition of the address signal; and a booster that has a plurality ofbooster circuits including first booster circuit and second boostercircuit. The first booster circuit being connected to the decoder andsupplying boosted voltage to a selected word line based on the activatedcontrol signal. The second booster circuit being input the deactivatedcontrol signal.

When each of the plurality of booster circuits are controlled to beactivated/deactivated, while one booster circuit is in a boost operationfor a word line, the other booster circuit can perform charging. Sincean apparent charging time can be shortened while sufficient charging forboosting is performed, high speed access to the memory cell can berealized. In particular, since the plurality of booster circuits arealternatively activated/deactivated, charging is normally completedevery timing at which address transition occurs, and boosted voltage canbe supplied to a word line.

The second booster circuit may charge, based on the deactivated controlsignal, an internal node of the second booster circuit up to a voltageobtained before the boosted voltage is output. According to theoperation, an apparent charging time is further shortened, and highspeed access to the memory cell can be realized.

The each of a plurality of booster circuits may include a plurality ofcapacitor elements, a first circuit that charges the plurality ofcapacitor elements when the control signal is deactivated; and a secondcircuit that outputs the boosted voltage obtained by series connectionof the plurality of charged capacitor elements when the control signalis activated. In this manner, a boost operation and a charging operationcan be switched to each other. According to this configuration, anapparent charging time can be shortened while sufficient charging forboosting is performed.

The semiconductor memory device may further include a detection circuitthat detects the transition of the address signal to output a detectionsignal, the control circuit may have a counter circuit that countstransitions of the detection signal output from the detection circuit toswitch the activated control signal and the deactivated control signal.According to this configuration, while one booster circuit is in a boostoperation for a word line, the other booster circuit can performcharging.

BRIEF DESCRIPTION OF THE DRAWINGS

This and other objects and features of the present invention will becomeclear from the subsequent description of a preferred embodiment thereofmade with reference to the accompanying drawings, in which like partsare designated by like reference numerals and in which:

FIG. 1A is a conventional circuit for boosting a word line;

FIG. 1B is a timing chart of the circuit in FIG. 1A;

FIG. 2 is a block diagram of a semiconductor memory device according tothe present invention;

FIG. 3 is an exeplary circuit diagram of a row decoder;

FIG. 4A is a circuit diagram of a control circuit;

FIG. 4B is a timing chart of an operation timing of the control circuit;

FIG. 5 is a circuit diagram of a booster circuit;

FIG. 6 is a timing chart of various signals when voltages are boosted intwo booster circuits;

FIG. 7 is a block diagram of a booster having four booster circuits; and

FIG. 8 is a timing chart of various signals obtained when voltages areboosted in four booster circuits.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An embodiment of the present invention will be described below withreference to the accompanying drawings.

As one characteristic feature of the present invention, a plurality ofbooster circuits each for boosting voltages of word lines are arranged,and, while one booster circuit is in a boost operation, other boostercircuit(s) can perform charging. According to this operation, since anapparent charging time can be shortened while sufficient charging forboosting the word lines is performed, high speed access to a memory cellcan be achieved.

FIG. 2 is a block diagram of semiconductor memory device 100 accordingto the present invention. Semiconductor memory device 100 is anonvolatile type semiconductor memory device, e.g., an EEPROM such as aflash memory. Semiconductor memory device 100 internally generatespotential which is different from that of power supply, boosts a voltageof a word line by using the potential, and performs operations such aselectrically writing, reading, erasing, and the like of data.

The configuration of semiconductor memory device 100 will be describedbelow. Semiconductor memory device 100 includes write/erase controlcircuit 1, data input/output buffer 2, sense amplifier 3, write circuit4, column decoder 5, address transition detector (ATD) generationcircuit 6, control circuit 7, booster 8, select gate decoder 9, sourceline driver 10, memory cell array 11, row decoder 12, address buffer 13,high-voltage generation circuit 14, well potential switching circuit 15,transfer gate 16, and column latches 17 and 18. For descriptiveconvenience, memory cell array 11 in one block is simplified with 2×2memory cells.

Write/erase control circuit 1 controls timings of a write operation andan erase operation, and voltages in these operations. Data input/outputbuffer 2 outputs data output from sense amplifier 3 to data terminalDQr, or outputs write data input from data terminal DQr to write circuit4. Sense amplifier 3 amplifies data of the memory cells in memory cellarray 11 input through Y-gate transistors Q1 and Q2, and outputs thedata to data input/output buffer 2. Write circuit 4 provides data inputfrom data input/output buffer 2 with column latches 17 and 18. Columndecoder 5 receives an output from address buffer 13 to select Y-gatetransistor Q1 or Q2. Select gate decoder 9 receives an output fromaddress buffer 13 to select one of select gates Q7 to Q10 in memory cellarray 11. Source line driver 10 includes N-channel MOS transistors Q3 toQ6. Source line driver 10 applies to a source line of the memory cell avoltage at ground level in a read operation and a negative voltage in anerase operation.

Memory cell array 11 includes memory cells Q11 to Q18 and a plurality ofselect gates Q7 to Q10. In memory cell array 11, data is written orerased in a memory cell selected by row decoder 12 and column decoder 5.Row decoder 12 receives an output from address buffer 13 to select apredetermined word line from the plurality of word lines. Address buffer13 receives an address signal from an address terminal Adr. The addresssignal is used to select a specific memory cell in memory cell array 11.Address buffer 13 further outputs a column address signal to columndecoder 5, and outputs a row address signal RAdr to row decoder 12.

High-voltage generation circuit 14 generates a positive or negative highvoltage required in writing or reading data based on a control signalfrom write/erase control circuit 1. High-voltage generation circuit 14functions as a selector. More specifically, high-voltage generationcircuit 14 selects an object component to which high-voltage generationcircuit 14 applies a voltage. High-voltage generation circuit 14generates and outputs high voltage to any one of select gate decoder 9,row decoder 12, well potential switch circuit 15, and column latches 17and 18 according to operation modes of semiconductor memory device 100.Well potential switch circuit 15 applies a negative high voltage to Pwell when erasing data in the memory cell, and applies a ground voltageto P well in other operation mode(s). Transfer gate 16 controlsconnections between column latches 17, 18 and bit lines. Column latches17 and 18 latch write operations.

ATD circuit 6 detects transition of an address signal input from theaddress terminal Adr to address buffer 13, and outputs an ATD signal.The “transition” means a change of an address of memory cell to beaccessed. The ATD signal becomes high level in a predetermined period oftime depending on a transition of the address signal. Control circuit 7outputs a control signal based on ATD signal from ATD generation circuit6. The control signal is sent to each of booster circuits constitutingbooster 8 (to be described later), is used to control the operationtimings of the booster circuits, and is also called as a booster circuitactivating signal. Booster 8 includes a plurality of booster circuits8-1, . . . , 8-n (n: integer). Each of the booster circuits boosts apower supply voltage and applies the boosted voltage to a word lineselected by row decoder 12 in data read operation.

Relationships of booster 8, row decoder 12, and the memory cells in thememory cell array 11 will be described below in more detail. FIG. 3 isan exemplary circuit diagram of row decoder 12. In this diagram, it isassumed that booster 8 has two booster circuits 8-1 and 8-2. Asdescribed above, ATD generation circuit 6 generates the ATD signal inresponse to address transition in address buffer 13 and sends the ATDsignal to control circuit 7. Control circuit 7 outputs booster circuitactivating signals BI1 and BI2. Booster circuits 8-1 and 8-2 receiveactivating signals BI1 and BI2 from control circuit 7, respectively.Booster circuits 8-1 and 8-2 start boost operations at times based onactivating signals BI1 and BI2, or output boosted voltages. Outputs BO1and BO2 of booster circuits 8-1 and 8-2 are connected to row decoder 12in common.

The row decoder 12 applies the boosted voltage from one of the boostercircuits 8-1 and 8-2 of the booster 8 to a word line selected based onthe row address signal RAdr. As far as the function is realized, theconfiguration of the row decoder 12 is arbitrarily determined. Forexample, the row decoder 12 in FIG. 3 may have a similar configurationto the conventional row decoder of FIG. 1A. More specifically, rowdecoder 12 receives the row address signal RAdr and converts the rowaddress signal RAdr into a plurality of internal row address signalswhich are all at high levels to output the plurality of internal rowaddress signals. Since the converting operation and a configurationtherefor are known by one skilled in the art, a description thereof willbe omitted.

On a word line Wn connected to memory cells Qn, n which are notaccessed, at least one of the internal row address signals becomes lowlevel. As a result, node 29 becomes the ground potential, and the wordline Wn becomes the ground potential, that is, non-selected state,thereby, the memory cell transistor Q is kept OFF state.

On the other hand, on a word line connected to memory cells Qn, n whichare accessed, all the internal row address signals become high levels,and the node 29 is electrically connected to connection nodes 27 and 28between the booster circuits 8-1 and 8-2 and the row decoder 12.Therefore, the word line Wn is electrically connected to the booster 8(selected state). As a result, a boosted voltage from the boostercircuit 8-1 or the booster circuit 8-2 is applied to the word line Wn,and the memory cell transistors Qn, n are turned on. The memory cellsQn, n can be accessed by using a bit line Bn.

The configurations and operations of control circuit 7 and boostercircuit 8-n will be described below. FIG. 4A is a circuit diagram whichshows a configuration of control circuit 7. FIG. 4B is a timing chartwhich shows an operation timing of control circuit 7. The configurationshown in FIG. 4A is a so-called ring counter. As shown in FIG. 4A,control circuit 7 includes two JK flipflops FF1 and FF2 and two outputterminals A and B corresponding to outputs Qs from the respectiveflipflops. Two activating signals BI1 and BI2 are output from outputterminals A and B.

The JK flipflop is reset by reset pulse RD and accepts states of inputsJ and K based on a timing of an input pulse to output a signal.According to the present invention, the input pulse corresponds to anATD signal output from ATD generation circuit 6 (FIG. 3). In theillustrated control circuit 7, the flipflops are reset by the resetpulse RD, and JK flipflop FF1 receives high- and low-level signals onthe input terminals J and K in response to an input pulse 1. As aresult, flipflop FF1 outputs 1 and 0 from output terminals Q and Q⁻. Theoutput signals are shifted to JK flipflop FF2 of the nest stage. Morespecifically, flipflop FF2 receives high- and low-level signals outputfrom flipflop FF1 on input terminals J and K, respectively, based onnext input pulse 2. As is apparent from FIG. 4B, after the reset pulseis input, one of the outputs A and B from flipflops FF is always at highlevel. The high-level signal is shifted, and sequentially output fromterminals A and B.

Subsequently, booster circuit 8-n (n: integer) will be described below.For example, it is assumed that booster circuit 8-n as shown in FIG. 5is used. As a matter of course, the present invention can also beperformed by another configuration.

FIG. 5 is a circuit diagram of booster circuit 8-n (n: integer). Boostercircuit 8-n outputs boosted voltage BO based on next input BI. Boostercircuits 8-n includes capacitor elements 41, 44-3, and 47-1 which areused for charge pumping, connection switch circuits 42 and 46 thatswitch whether capacitor element 41 and 44-3 are connected in serieswith each other or not, and charging switch circuit 44 that chargescapacitor elements 41 and 44-3. Booster circuit 8-n includes powersupply 47-2 that charges the capacitor elements, and transistor 49 forswitching whether the voltage of a line VB as boosted voltage BO. Theconfigurations of connection switch circuits 42 and 46 are equal to eachother. Capacitor element 41, connection switch circuit 42, chargingswitch circuit 44, and connection switch circuit 46 are connected inseries with each other in the order named. Inverted signal 48 of inputsignal BI is input to circuits 42, 44, and 46. Circuits 42, 44, and 46adjust a voltage applied to the gate of transistor 49 depending onwhether inverted signal 48 is in high level or in low level. The detailsof the adjustment will be described below.

It is considered that inverted signal 48 becomes high level by low-levelinput signal BI. In this case, in connection switch circuit 42,transistor 42-1 is turned on, and transistor 42-3 is also turned on.Since the potential of capacitor element 41 on input BI side is at lowlevel, power supply 42-4 starts electrifying capacitor element 41. Notethat transistor 42-2 is in an off state. In charging switch circuit 44,transistor 44-1 is turned on, both electrodes of capacitor element 43has the ground potential. In connection switch circuit 46, whentransistors 46-1 and 46-3 are turned on, power supply 46-4 startscharging capacitor element 44-3. Since inverted signal 48 is at highlevel, transistor 43 is turned on, and the gate of transistor 49 has theground potential. Therefore, when input signal BI is at low level,charging capacitor elements 41 and 44-3 is started. At this time, it isnoted that charge pump capacitor element 47-1 is also charged by powersupply 47-2.

It is considered that inverted signal 48 becomes low level by high-levelinput signal BI. In this case, in connection switch circuit 42,transistor 42-2 is turned on, and transistor 42-1 and transistor 42-3are turned off. In charging switch circuit 44, transistor 44-2 is turnedon. As a result, capacitor elements 41 and 44-3 are connected in serieswith each other. More specifically, charging switch circuit 44 switcheswhether capacitor element 41 and capacitor element 44-3 are connected inseries with each other or not by an on/off operation of transistor 44-2based on inverted signal 48. In the connection switch circuit 46,transistor 46-2 is turned on, while transistor 46-3 is turned off.Therefore, input signal BI is at high level, capacitor elements 41 and44-3 are connected in series with each other. Furthermore, at this time,since inverted signal 48 is at low level, transistor 45 is set in an ONstate. Therefore, sufficiently larger voltage than a threshold voltageis obtained by the series connection of capacitor elements 41 and 44-3and is applied to the gate of transistor 49. As a result, transistor 49is turned on, a boosted voltage which is not decreased due to thethreshold voltage is output by charge pump capacitor element 47-1.

The operations of ATD generation circuit 6, control circuit 7, andbooster circuits 8-1 and 8-2 of booster 8 based on the configurationsdescribed with reference to FIGS. 3 to 5 will be described below. FIG. 6is a timing chart of various signals obtained when voltages are boostedin the two booster circuits. Signals BI1 and BI2 are shown in FIG. 3,and a node VB in the booster circuits 8-1 and 8-2 is shown in FIG. 5.Control circuit 7 (FIG. 3) receives an ATD signal from ATD generationcircuit 6, and inverts activating signals BI1 and BI2 at a trailing edgeof the ATD signal. In FIG. 3, the trailing edge of the ATD signalappears at times T1 and T2. At time T1, the control circuit makes thelevel of signal BI1 high, and activates booster circuit 8-1 (FIG. 5).High-level control signal output from the control circuit is also calledas an activating signal. An operation performed at this time is asdescribed with reference to FIG. 5. As a result, the voltage of the nodeVB of booster circuit 8-1 (FIG. 5) is boosted. As is apparent from FIG.6, the voltage of the node VB is boosted to be higher than a powersupply voltage Vcc. The boosted voltage is applied to a selected wordline.

When an address to be accessed is changed to select a word line that isdifferent from the word line selected at the present, ATD generationcircuit 6 (FIG. 3) generates a new ATD signal and sends the ATD signalto control circuit 7 (FIG. 3). Control circuit 7 (FIG. 3) makes thelevel of signal BI2 high at the trailing edge of the ATD signal at timeT2, and activates booster circuit 8-2 (FIG. 3). The voltage boosted bybooster circuit 8-2 (FIG. 3) is applied to a newly selected word line.At this time, the level of signal BI1 is set to low, and booster circuit8-1 (FIG. 5) which has been activated is deactivated. Thereafter,inactive booster circuit 8-1 (FIG. 5) performs a charging operation.More specifically, the voltage of the node VB of booster circuit 8-1(FIG. 5) is smaller than the power supply voltage Vcc: Therefore, thenode VB is charged to have a voltage equal to the power supply voltageVcc. As a result, booster 8 (FIG. 3) including booster circuits 8-1 and8-2 can output sufficiently boosted voltages every transition of the ATDsignal.

As described above, since the plurality of booster circuits arealternately activated/deactivated, sufficient times for charging thecapacitors in each booster circuit can be secured. The charging isapparently normally completed every timing at which address transitionoccurs, and a boosted voltage can be supplied to a word line. For thisreason, high speed access to a memory cell can be realized.

In FIG. 3, although it is described that booster 8 includes two boostercircuits, the number of booster circuits can be larger. FIG. 7 is ablock diagram that shows a configuration in which booster 8 has fourbooster circuits 8-1 to 8-4. The configuration in FIG. 7 is differentfrom that in FIG. 3 in that the four booster circuits are arranged. Dueto such difference, in FIG. 7, the control circuit 7 generates controlsignals BI1 to BI4, and row decoder 12 receives output from the fourbooster circuits. Since the configuration in FIG. 7 is equal to that inFIG. 3 except for the above points, a description of equivalent elementswill be omitted. FIG. 8 shows a timing chart of various signals obtainedwhen voltages are boosted in the four booster circuits. As describedwith reference to FIG. 6, control circuit 7 (FIG. 7) outputs signals BI1to BI4, the high levels of which are sequentially shifted depending onthe trailing edge of an ATD signal. Booster circuits 8-1 to 84 outputboosted voltages when the corresponding signals BI1 to BI4 become highlevels. On the other hand, respective booster circuits 8-1 to 8-4 startcharging internal capacitors when the corresponding signals BI1 to BI4become low levels. In this manner, when a large number of boostercircuits are sequentially activated, times required for charging thecapacitors can be further shortened. Therefore, very high speed accessto a memory cell can be achieved.

The invention being thus described, it will be obvious that the same maybe varied in many ways. Such variations are not to be regarded as adeparture from the spirit and scope of the invention, and all suchmodifications as would be obvious to one skilled in the art are intendedto be included within the scope of the following claims.

What is claimed is:
 1. A semiconductor memory device comprising: a plurality of memory cells; a plurality of word lines to which voltages are applied to select the plurality of memory cells; a decoder for selecting one of the plurality of word lines based on an address signal representing an address of one of the plurality of memory cells to be accessed; a control circuit for outputting an activated control signal and an deactivated control signal according to a transition of the address signal; and a booster that has a plurality of booster circuits including first booster circuit and second booster circuit, said first and second booster circuits being connected to the decoder, performing a charging operation and supplying boosted voltage to a selected word line, wherein said first and second booster circuits are configured to perform the charging operation when receiving the deactivated control signal from the control circuit, and supply the boosted voltage to the selected word line when receiving the activated control signal from the control circuit, and the control circuit is configured to output the activated control signal and the deactivated control signal to said first and second booster circuits so that one of said first and second booster circuits performs the charging operation, while the other supplies the boosted voltage to the selected word line.
 2. A semiconductor memory device according to claim 1, wherein the second booster circuit charges, based on the deactivated control signal, an internal node of the second booster circuit up to a voltage obtained before the boosted voltage is output.
 3. A semiconductor memory device according to claim 2, wherein each of the plurality of booster circuits comprises: a plurality of capacitor elements; a first circuit configured for charging the plurality of capacitor elements when the control signal is deactivated; and a second circuit configured for outputting the boosted voltage obtained by series connection of the plurality of charged capacitor elements when the control signal is activated.
 4. A semiconductor memory device according to claim 3, further comprising a detection circuit that detects the transition of the address signal to output a detection signal, wherein the control circuit has a counter circuit that counts transitions of the detection signal output from the detection circuit to switch the activated control signal and the deactivated control signal. 